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MOTOROLA
Freescale SEMICONDUCTOR TECHNICAL DATA Semiconductor, Inc.
Order Number: MPC99J93/D Rev 1, 08/2003
Product Preview Intelligent Dynamic Clock Switch (IDCS) PLL Clock Driver
The MPC99J93 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals from which it generates 5 new differential LVPECL clock outputs. Two of the output pairs regenerate the input signals frequency and phase while the other three pairs generate 2x, phase aligned clock outputs. Features: * Fully Integrated PLL
MPC99J93
Freescale Semiconductor, Inc...
FA SUFFIX 32--LEAD LQFP PACKAGE CASE 873A
* * * * *
Intelligent Dynamic Clock Switch LVPECL Clock Outputs LVCMOS Control I/O 3.3V Operation 32--Lead LQFP Packaging
Functional Description The MPC99J93 Intelligent Dynamic Clock Switch (IDCS) circuit continuously monitors both input CLK signals. Upon detection of a failure (CLK stuck HIGH or LOW for at least 1 period), the INP_BAD for that CLK will be latched (H). If that CLK is the primary clock, the IDCS will switch to the good secondary clock and phase/frequency alignment will occur with minimal output phase disturbance. The typical phase bump caused by a failed clock is eliminated. (See Application Information section).
PLL_En Clk_Selected Inp1bad Inp0bad Man_Override Alarm_Reset Sel_Clk CLK0 CLK0 CLK1 CLK1 Ext_FB Ext_FB MR OR
Dynamic Switch Logic Qb0 Qb0 Qb1 Qb1 /2 PLL 200 -- 360 MHz /4 Qb2 Qb2 Qa0 Qa0 Qa1 Qa1
Figure 1. Block Diagram
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. E Motorola Inc. 2003
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VCC VCC 17 16 15 14 VCC Inp0bad Inp1bad Clk_Selected GND Ext_FB Ext_FB GND 13 12 11 10 9 1 2 3 4 5 6 7 8 GND Qb0 Qb0 Qb1 Qb1 Qb2 19 CLK1 Qb2 18 CLK1
24 Qa1 Qa1 Qa0 Qa0 VCC VCC_PLL Man_Override 25 26 27 28 29 30 31 32
23
22
21
20
MPC99J93
Freescale Semiconductor, Inc...
PLL_En
Alarm_Reset
CLK0
CLK0
Figure 2. 32-Lead Pinout (Top View) Table 1. Pin Descriptions
Pin Name CLK0, CLK0 CLK1, CLK1 Ext_FB, Ext_FB Qa0:1, Qa0:1 Qb0:2, Qb0:2 Inp0bad Inp1bad Clk_Selected Alarm_Reset Sel_Clk Manual_Override PLL_En MR VCCA VCC GNDA GND I/O LVPECL Input LVPECL Input LVPECL Input LVPECL Output LVPECL Output LVCMOS Output LVCMOS Output LVCMOS Output LVCMOS Input LVCMOS Input LVCMOS Input LVCMOS Input LVCMOS Input Power Supply Power Supply Power Supply Power Supply Pin Definition Differential PLL clock reference (CLK0 pulldown, CLK0 pullup) Differential PLL clock reference (CLK1 pulldown, CLK1 pullup) Differential PLL feedback clock (Ext_FB pulldown, Ext_FB pullup) Differential 1x output pairs. Connect one QAx pair to Ext_FB. Differential 2x output pairs Indicates detection of a bad input reference clock 0 with respect to the feedback signal. The output is active HIGH and will remain HIGH until the alarm reset is asserted Indicates detection of a bad input reference clock 1 with respect to the feedback signal. The output is active HIGH and will remain HIGH until the alarm reset is asserted `0' if clock 0 is selected, `1' if clock 1 is selected `0' will reset the input bad flags and align Clk_Selected with Sel_Clk. The input is "one--shotted" (50k pullup) `0' selects CLK0, `1' selects CLK1 (50k pulldown) `1' disables internal clock switch circuitry (50k pulldown) `0' bypasses selected input reference around the phase--locked loop (50k pullup) `0' resets the internal dividers forcing Q outputs LOW. Asynchronous to the clock (50k pullup) PLL power supply Digital power supply PLL ground Digital ground
2
Sel_Clk
MR
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Table 2. ABSOLUTE MAXIMUM RATINGSa
Symbol VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage temperature -65 Characteristics Min -0.3 -0.3 -0.3 Max 3.9 VCC+0.3 VCC+0.3 20 50 125 Unit V V V mA mA C
MPC99J93
Condition
a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied.
Table 3. GENERAL SPECIFICATIONS
Symbol Characteristics Output termination voltage ESD Protection (Machine model) ESD Protection (Human body model) ESD Protection (Charged device model Latch-up immunity Input Capacitance Thermal resistance junction to ambient JESD 51-3, single layer test board 175 1500 1000 100 4.0 83.1 73.3 68.9 63.8 57.4 59.0 54.4 52.5 50.4 47.8 23.0 86.0 75.4 70.9 65.3 59.6 60.6 55.7 53.8 51.5 48.8 26.3 Min Typ VCC - 2 Max Unit V V V V mA pF C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W Inputs Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min MIL-SPEC 883E Method 1012.1 Condition VTT MM HBM CDM LU CIN JA
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JESD 51-6, 2S2P multilayer test board
JC TJ
Thermal resistance junction to case Operating junction temperaturea (continuous operation) MTBF = 9.1 years
110
C
a. Operating junction temperature impacts device life time. Maximum continuous operating junction temperature should be selected according to the application life time requirements (See application note AN1545 for more information). The device AC and DC parameters are specified up to 110C junction temperature allowing the MPC99J93 to be used in applications requiring industrial temperature range. It is recommended that users of the MPC99J93 employ thermal modeling analysis to assist in applying the junction temperature specifications to their particular application.
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Characteristics Min 2.0 Typ Max VCC + 0.3 0.8 100 2.0 0.55 Ext_FB)b 0.1 VCC-1.8 1.3 VCC-0.3 100 VCC-1.20 VCC-1.90 VCC-0.95 VCC-1.75 VCC-0.70 VCC-1.45 180 15 V V A V V Differential operation Differential operation VIN=VCC or GND Termination 50 to VTT Termination 50 to VTT GND pins VCC_PLL pin Voltaged Unit V V A V V VIN=VCC or GND IOH=-24 mA IOL= 24 mA Condition
Table 4. DC CHARACTERISTICS (VCC = 3.3V 5%, TA = --40 to +85C)
Symbol VIH VIL IIN VOH VOL VPP VCMR IIN LVCMOS control inputs (MR, PLL_En, Sel_Clk, Man_Override, Alarm_Reset) Input High Voltage Input Low Voltage Input Currenta
LVCMOS control outputs (Clk_selected, Inp0bad, Inp1bad) Output High Voltage Output Low Voltage DC Differential Input Voltagec Differential Cross Point Input Currenta
LVPECL clock inputs (CLK0, CLK1,
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LVPECL clock outputs (QA[1:0], QB[2:0]) VOH VOL IGND ICC_PLL a. b. c. d. Output High Voltage Output Low Voltage
Supply Current Maximum Power Supply Current Maximum PLL Supply Current mA mA
Inputs have internal pull-up/pull-down resistors affecting the input current. Clock inputs driven by differential LVPECL compatible signals. VPP is the minimum differential input voltage swing required to maintain AC characteristics. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification.
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Table 5. AC Characteristics (VCC = 3.3V 5%, TA = --40C to +85C)a
Symbol fref fVCO fMAX frefDC t() VPP VCMR tsk(O) per/cycle VCO Frequency Characteristics Input Reference Frequency Rangeb Output Frequency Reference Input Duty Cycle Propagation Delay Differential input voltaged Differential input crosspoint Output-to-output Skew Rate of change of period voltagee SPO, static phase CLK0, CLK1 to any Q (peak-to-peak) within QA[2:0] or QB[1:0] within device QA[1:0]f QB[2:0]f QA[1:0]g QB[2:0]g 45 RMS (1 ) 0.05 20 10 200 100 50 25 10 0.70 offsetc /4 feedback /4 feedback QA[1:0] QB[2:0] Min 50 200 50 100 25 -0.15 0.9 0.25 VCC-1.7 Typ Max 90 360 90 180 75 +0.17 1.8 1.3 VCC-0.3 50 80 50 25 400 200 55 Unit MHz MHz MHz MHz % ns ns V V ps ps ps ps ps ps % ps ms ns
MPC99J93
Condition PLL locked PLL locked
PLL_EN=1 PLL_EN=0
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DC tJIT(CC) tLOCK tr, tf a. b. c. d.
Output Duty Cycle Cycle-to-Cycle Jitter Maximum PLL Lock Time Output Rise/Fall Time
20% to 80%
AC characteristics apply for parallel output termination of 50 to VCC - 2V. The input reference frequency must match the VCO lock range divided by the feedback divider ratio (FB): fref = fVCO / FB. CLK0, CLK1 to Ext_FB. VPP is the minimum differential input voltage swing required to maintain AC characteristics including SPO and device-to-device skew. Applicable to CLK0, CLK1 and Ext_FB. e. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC) range and the input swing lies within the V PP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the SPO, device and part-topart skew. Applicable to CLK0, CLK1 and Ext_FB. f. Specification holds for a clock switch between two input signals (CLK0, CLK1) no greater than 400 ps out of phase. Delta period change per cycle is averaged over the clock switch excursion. g. Specification holds for a clock switch between two input signals (CLK0, CLK1) at any phase difference (180_). Delta period change per cycle is averaged over the clock switch excursion.
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APPLICATIONS INFORMATION
The MPC99J93 is a dual clock PLL with on--chip Intelligent Dynamic Clock Switch (IDCS) circuitry. Definitions primary clock: The input CLK selected by Sel_Clk. secondary clock: The input CLK NOT selected by Sel_Clk. PLL reference signal: The CLK selected as the PLL reference signal by Sel_Clk or IDCS. (IDCS can override Sel_Clk). Status Functions Clk_Selected: Clk_Selected (L) indicates CLK0 is selected as the PLL reference signal. Clk_Selected (H) indicates CLK1 is selected as the PLL reference signal. INP_BAD: Latched (H) when it's CLK is stuck (H) or (L) for at least one Ext_FB period (Pos to Pos or Neg to Neg). Cleared (L) on assertion of Alarm_Reset.
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Control Functions Sel_Clk: Sel_Clk (L) selects CLK0 as the primary clock. Sel_Clk (H) selects CLK1 as the primary clock. Alarm_Reset: Asserted by a negative edge. Generates a one--shot reset pulse that clears INPUT_BAD latches and Clk_Selected latch. PLL_En: While (L), the PLL reference signal is substituted for the VCO output. MR: While (L), internal dividers are held in reset which holds all Q outputs LOW. Man Override (H) (IDCS is disabled, PLL functions normally). PLL reference signal (as indicated by Clk_Selected) will always be the CLK selected by Sel_Clk. The status function INP_BAD is active in Man Override (H) and (L). Man Override (L) (IDCS is enabled, PLL functions enhanced). The first CLK to fail will latch it's INP_BAD (H) status flag and select the other input as the Clk_Selected for the PLL reference clock. Once latched, the Clk_Selected and INP_BAD remain latched until assertion of Alarm_Reset which clears all latches (INP_BADs are cleared and Clk_Selected = Sel_Clk). NOTE: If both CLKs are bad when Alarm_Reset is asserted, both INP_BADs will be latched (H) after one Ext_FB period and Clk_Selected will be
latched (L) indicating CLK0 is the PLL reference signal. While neither INP_BAD is latched (H), the Clk_Selected can be freely changed with Sel_Clk. Whenever a CLK switch occurs, (manually or by IDCS), following the next negative edge of the newly selected PLL reference signal, the next positive edge pair of Ext_FB and the newly selected PLL reference signal will slew to alignment. To calculate the overall uncertainty between the input CLKs and the outputs from multiple MPC99J93's, the following procedure should be used. Assuming that the input CLKs to all MPC9993's are exactly in phase, the total uncertainty will be the sum of the static phase offset, max I/O jitter, and output to output skew. During a dynamic switch, the output phase between two devices may be increased for a short period of time. If the two input CLKs are 400ps out of phase, a dynamic switch of an MPC99J93 will result in an instantaneous phase change of 400ps to the PLL reference signal without a corresponding change in the output phase (due to the limited response of the PLL). As a result, the I/O phase of a device, undergoing this switch, will initially be 400ps and diminish as the PLL slews to its new phase alignment. This transient timing issue should be considered when analyzing the overall skew budget of a system. Hot insertion and withdrawal In PECL applications, a powered up driver will experience a low impedance path through an MPC99J93 input to its powered down VCC pins. In this case, a 100 ohm series resistance should be used in front of the input pins to limit the driver current. The resistor will have minimal impact on the rise and fall times of the input signals. Acquiring Frequency Lock 1. While the MPC99J93 is receiving a valid CLK signal, assert Man_Override HIGH. 2. The PLL will phase and frequency lock within the specified lock time. 3. Apply a HIGH to LOW transition to Alarm_Reset to reset Input Bad flags. 4. De--assert Man_Override LOW to enable Intelligent Dynamic Clock Switch mode.
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OUTLINE DIMENSIONS
FA SUFFIX PLASTIC LQFP PACKAGE CASE 873A--03 ISSUE B
4X
MPC99J93
D1
PIN 1 INDEX
6
0.20 H A--B D e/2
25
D1/2
32
3
A, B, D
1
E1/2 A 6 E1
B E
DETAIL G 8 17
F 4 F E/2 DETAIL G
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DATUMS A, B, AND D TO BE DETERMINED AT DATUM PLANE H. 4. DIMENSIONS D AND E TO BE DETERMINED AT SEATING PLANE C. 5. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED THE MAXIMUM b DIMENSION BY MORE THAN 0.08--mm. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION: 0.07--mm. 6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25--mm PER SIDE. D1 AND E1 ARE MAXIMUM PLASTIC BODY SIZE DIMENSIONS INCLUDING MOLD MISMATCH. 7. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 8. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.1--mm AND 0.25--mm FROM THE LEAD TIP.
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7
9
D D 4
D/2
4X
0.20 C A--B D
H
SEATING PLANE
28X
e
32X
0.1 C
C
DETAIL AD
PLATING BASE METAL
b1 c b R R2 R R1 A A2 0.25
GAUGE PLANE
c1 5 8
DIM A A1 A2 b b1 c c1 D D1 e E E1 L L1 1 R1 R2 S
8X
( 1_)
0.20
M
C A--B D
SECTION F-F
A1
(S) (L1) DETAIL AD
L
_
MILLIMETERS MIN MAX 1.40 1.60 0.05 0.15 1.35 1.45 0.30 0.45 0.30 0.40 0.09 0.20 0.09 0.16 9.00 BSC 7.00 BSC 0.80 BSC 9.00 BSC 7.00 BSC 0.50 0.70 1.00 REF 0_ 7_ 12 _REF 0.08 0.20 0.08 -----0.20 REF
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Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. MOTOROLA and the Stylized M Logo are registered in the US Patent and Trademark Office. All other product or service names are the property of their respective owners. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. E Motorola Inc. 2003 HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution P.O. Box 5405, Denver, Colorado 80217 1--800--521--6274 or 480--768--2130 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3--20--1, Minami--Azabu, Minato--ku, Tokyo 106--8573, Japan 81--3--3440--3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong 852--26668334 HOME PAGE: http://motorola.com/semiconductors
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MPC99J93/D

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